Using SPA with a Custom Target — Embedded Design Tutorials 2022.1 documentation (2024)

Instantiate APM IP¶

The Zynq UltraScale+ MPSoC has some hardened APM IP blocks in the PS. They can be used to monitor the AXI performance for DDR, CCI, OCM and LPD. Check the yellow blocks in the following diagram.

The Vitis IDE performance analysis can make use of the PS built-in APM (blocks in yellow in the diagram above) as well as user-instantiated APM IPs in the PL. You can instantiate the APM in PL to monitor the performance of AXI interfaces between PS and PL for Zynq-7000 devices and Zynq UltraScale+ MPSoCs.

Figure 44: AXI Performance Monitor

The previous figure shows how an instance of an APM appears in a Vivado® Design Suite IP integrator block diagram, as well as its configuration panel. The following steps give an example of adding an IP, connecting it, and configuring it. For more information about the Vivado IP Integrator, see the Vivado Design Suite Tutorial: Embedded Processor Hardware Design UG940 and Zynq UltraScale+ MPSoC Embedded Design Tutorial UG1209.

1. Add the APM IP to your Vivado design:

   • In the IP integrator block diagram, click the Add IP button.

   • Search for AXI Performance Monitor and double-click it.

2. Customize the APM IP.

   • Double-click the APM to open the Re-customize IP dialog box. In this dialog box, set the following:

     • Set APM Mode to Profile.

     • Set the Number of Monitor interfaces to the number of interfaces you want to monitor. For this example, choose 5.

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     • Click OK to close the window.

3. Connect the APM to your design:

   • Connect S_AXI to the General Purpose AXI Interface on the Processing System (via AXI interconnect). You can use this interface to read and write APM registers from PS.

   • Connect s_axi_aclk and s_axi_aresetn to the clock and reset associated with S_AXI above.

   • Connect the SLOT_x_AXI ports (where x=0…4) to any AXI interfaces you want to monitor, such as S_AXI_HPx, and ACP on Zynq-7000 devices, and S_AXI_HPx, S_AXI_HPCx, or S_AXI_ACE on Zynq UltraScale+ MPSoCs.

   • Connect all inputs slot_x_axi_aclk and slot_x_axi_aresetn to the appropriate clocks and resets. They are used for the monitor AXI interfaces.

   • Connect core_aclk and core_aresetn to the clock/reset with the highest clock frequency.

Instantiate AXI Traffic Generator IP¶

If you have not implemented your traffic IP during the system performance evaluation, you can use the AXI Traffic Generator to mimic its throughput to test the system performance. The AXI Traffic Generator is optional to SPA.

Follow these steps to add, configure, and connect the ATG IP to your Vivado design.

1. Add ATG IP to your Vivado design:

   • In the IP integrator block diagram, click the Add IP button.

   • Search for AXI Traffic Generator and double-click it.

2. Customize the ATG IP

   Note: You can use most of the default ATG settings. Note that the master interface of the ATG should match the width of the AXI interface test.

   • Double-click the ATG to open the Re-customize IP dialog box. In this dialog box, set the following:

     • Set Data Width of Master Interface section to the AXI interface width you want to test. For this example, set it to 128. Change the settings accordingly if the AXI interface you want to monitor has some special settings.

     • Click OK to close the window.

3. Connect the ATG IP to your design by doing the following:

   • Connect S_AXI to the General Purpose AXI Interface on the PS (via AXI interconnect). You can use this interface to read and write APM registers from PS.

   • Connect s_axi_aclk and s_axi_aresetn to the clock and reset associated with S_AXI above.

   • Connect the M_AXI ports to any AXI interfaces you want to test, such as S_AXI_HPx, and ACP on Zynq-7000 devices and S_AXI_HPx_FPD, S_AXI_HPCx, or S_AXI_ACE on Zynq UltraScale+ MPSoCs (through AXI Interconnect or AXI SmartConnect).

   • Connect irq_out to the PL-PS IRQ input of PS. You can connect it through a Concat IP, if there are multiple interrupt inputs to the PS.

Export to Vitis IDE¶

To configure the Vitis IDE to read the hardware design, generate a platform, and read the APM and ATG related information, follow these steps:

• In the Flow Navigator pane, click Generate Bitstream.

• After the bitstream is generated, export the design using the File → Export→ Export Hardware → Include bitstream.

• Select the name and path to save this XSA.

• After exporting the design, launch the Vitis IDE by selecting Tools → Launch Vitis IDE.

The following up steps in Vitis IDE are described in Monitoring a Custom Target Chapter.